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SP6132
Wide Input, 300KHz Synchronous PWM Controller
FEATURES
3V to 12V Step Down Achieved Using Dual Input 2A to 15A Ouput Capability Highly Integrated Design, Minimal Components UVLO Detects Both VCC and VIN Short Circuit Protection with Auto-Restart On-Board 1.5 sink (2 source) NFET Drivers Wide BW Amp Allows Type II or III Compensation Programmable Soft Start Fast Transient Response High Efficiency: Greater than 95% Possible A Synchronous Start-Up into a Pre-Charged Output Small 10-Pin MSOP Package
VCC 1 GL 2 GND 3 VFB 4 COMP 5
10 BST
SP6132
10 Pin MSOP
9 GH 8 SWN 7 SS 6 UVIN
Now Available in Lead Free Packaging
DESCRIPTION
The SP6132 is wide input, synchronous step-down switching controller optimized for high efficiency. The part is designed to be especially attractive for dual supply, 12V step down with 5V used to power the controller. This lower VCC voltage minimizes power dissipation in the part. The SP6132 is designed to drive a pair of external NFETs using a fixed 300kHz frequency, PWM voltage mode architecture. Protection features include UVLO, thermal shutdown and output short circuit protection. The SP6132 is available in the cost and space saving 10-pin MSOP.
TYPICAL APPLICATION CIRCUIT
VIN 12V C1 22F 16V C2 22F 16V GND C1, C2 Ceramic 1210 X5R
8765
4 123
QT FDS7088N3 21A, 5m
VCC
DBST MBR0530
1 VCC
U1
BST 10 2 3 4 5 GL SP6132 GH 9 GND VFB COMP SWN 8 SS 7 UVIN 6
R3 221k, 1% UVIN R4 100k, 1%
CVCC 10F 6.3V CVCC Ceramic 0805 X5R C7 0.1F
GND 3
CBST 1F 10V R5 5.11, 1%
4
8765
L1 SC5018-2R7M 2.7H @ 12A
DCR=4.30m
RZ3 4.64k, 1% C3 47F 6.3V C4 47F 6.3V CZ3 220pF
VOUT 3.3V 0 - 10 A R1 68.1k, 1%
SS
123
QB FDS7088N3 21A, 5m
CZ2
RZ2
CSS 47nF
GND2 C3, C4 Ceramic 1210 X5R R2 21.5k, 1%
1500pF 27.4k, 1% CP1 CF1 100pF 22pF fs=300Khz
ALL RESISTORS AND CAPS ARE 0603 UNLESS OTHERWISE SPECIFIED Q1, Q2 BOTTOM SIDE DRAIN CONTACT
Date: 8/4/04
SP6132 Wide Input, 300KHz Synchronous PWM Controller
(c) Copyright 2004 Sipex Corporation
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ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. VCC .................................................................................................. 7V BST ............................................................................................... 22V BST-SWN ......................................................................... -0.3V to 7V SWN ................................................................................... -1V to 15V GH ......................................................................... -0.3V to BST+0.3V GH-SWN ......................................................................................... 7V All other pins .......................................................... -0.3V to VCC+0.3V Peak Output Current < 10us GH,GL ............................................................................................. 2A Storage Temperature .................................................. -65C to 150C Power Dissipation .......................................................................... 1W Lead Temperature (Soldering, 10 sec) ...................................... 300C ESD Rating .......................................................................... 2kV HBM Thermal Resistance ............................................................. 41.9C/W
ELECTRICAL SPECIFICATIONS
Unless otherwise specified: 0C < TAMB < 70C, 4.5V < VCC < 5.5V, BST=VCC,SWN = GND = 0V, UVIN = 3.0V, CVCC = 10F, CCOMP = 0.1F, CGH = CGL = 3.3nF, CSS = 50nF, Typical measured at VCC=5V. The denotes the specifications which apply over the -40C to 85C temperature range, unless otherwise specified.
PARAMETER QUIESCENT CURRENT VCC Supply Current BST Supply Current PROTECTION: UVLO VCC UVLO Start Threshold VCC UVLO Hysteresis UVIN Start Threshold UVIN Hysteresis UVIN Input Current ERROR AMPLIFIER REFERENCE Error Amplifier Reference Error Amplifier Reference Over Line and Temperature Error Amplifier Transconductance Error Amplifier Gain COMP Sink Current COMP Source Current VFB Input Bias Current Internal Pole COMP Clamp COMP Clamp Temp. Coefficient Ramp Amplitude RAMP Offset RAMP Offset Temp. Coefficient GH Minimum Pulse Width Maximum Controllable Duty Ratio Maximum Duty Ratio Internal Oscillator Frequency
MIN
TYP 1.5 0.2
MAX 3 0.4 4.5 300 2.65 400 1
UNITS mA mA V mV V mV A

CONDITIONS VFB =0.9V (No switching) VFB =0.9V (No switching)
4.00 100 2.3 200
4.25 200 2.5 300
UVIN =3.0V
0.792 0.788
0.800 0.800 6 60 150 150 50 4 2.5 -2
0.808 0.812
V V ms dB A A
2X Gain Config., Measure VFB; VCC = 5V, T=25C
No Load VFB = 0.9V, COMP = 0.9V VFB = 0.7V, COMP = 2.2V
200
nA MHz V mV/C
VFB = 0.8V VFB=0.7V, TA = 25C
CONTROL LOOP: PWM COMPARATOR, RAMP & LOOP DELAY PATH 0.92 1.1 1.1 -2 90 92 100 240 300 360 97 180 1.28 V V mV/C ns % % kHz

TA = 25C, RAMP COMP until GH starts switching
Maximum Duty Ratio Measured just before pulse skipping begins Valid for 20 Cycles
Date: 8/4/04
SP6132 Wide Input, 300KHz Synchronous PWM Controller
(c) Copyright 2004 Sipex Corporation
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ELECTRICAL SPECIFICATIONS: Continued
Unless otherwise specified: 0C < TAMB < 70C, 4.5V < VCC < 5.5V, BST=VCC,SWN = GND = 0V, UVIN = 3.0V, CVCC = 10F, CCOMP = 0.1F, CGH = CGL = 3.3nF, CSS = 50nF, Typical measured at VCC=5V. The denotes the specifications which apply over the -40C to 85C temperature range, unless otherwise specified.
PARAMETER TIMERS: SOFTSTART SS Charge Current: SS Discharge Current: Short Circuit Threshold Voltage Hiccup Timeout Number of Allowable Clock Cycles at 100% Duty Cycle Minimum GL Pulse After 20 Cycles Thermal Shutdown Temperature Thermal Recovery Temperature Thermal Hysteresis OUTPUT: NFET GATE DRIVERS GH & GL Rise Times GH & GL Fall Times GL to GH Non Overlap Time SWN to GL Non Overlap Time GH & GL Pull Down Resistance Driver Pull Down Resistance Driver Pull Up Resistance
MIN
TYP 10
MAX
UNITS A mA
CONDITIONS
1 0.2 0.25 200 20 0.5 145 135 10 35 30 45 25 15 50 1.5 2.5 50 40 70 40 85 1.9 3.0 0.3
Fault Present, SS = 0.2V Measured VREF (0.8V) - VFB VFB = 0.5V VFB = 0.7V VFB = 0.7V
PROTECTION: SHORT CIRCUIT & THERMAL V ms Cycles Cycles C C C ns ns ns ns K

Measured 10% to 90% Measured 90% to 10% GH & GL Measured at 2.0V Measured SWN = 100mV to GL = 2.0V Note 1 Note 1
PIN DESCRIPTION
PIN # 1 2 3 4 PIN NAME DESCRIPTION VCC Bias Supply Input. Connect to external 5V supply. Used to power internal circuits and low side gate driver. GL High current driver output for the low side NFET switch. It is always low if GH is high or during a fault. Resistor pull down ensure low state at low voltage. GND Ground Pin. The control circuitry of the IC and lower power driver are referenced to this pin. Return separately from other ground traces to the (-) terminal of COUT. VFB Feedback Voltage and Short Circuit Detection pin. It is the inverting input of the Error Amplifier and serves as the output voltage feedback point for the Buck Converter. The output voltage is sensed and can be adjusted through an external resistor divider. Whenever VFB drops 0.25V below the positive reference, a short circuit fault is detected and the IC enters hiccup mode. COMP Output of the Error Amplifier. It is internally connected to the inverting input of the PWM comparator. An optimal filter combination is chosen and connected to this pin and either ground or VFB to stabilize the voltage mode loop. UVIN UVLO input for VIN voltage. Connect a resistor divider between VIN and UVIN to set minimum operating voltage. SS Soft Start. Connect an external capacitor between SS and GND to set the soft start rate based on the 10A source current. The SS pin is held low via a 1mA (min) current during all fault conditions. SWN Lower supply rail for the GH high-side gate driver. Connect this pin to the switching node at the junction between the two external power MOSFET transistors. GH High current driver output for the high side NFET switch. It is always low if GL is high or during a fault. Resistor pull down ensure low state at low voltage. BST High side driver supply pin. Connect BST to the external boost diode and capacitor as shown in the Typical Application Circuit on page 1. High side driver is connected between BST pin and SWN pin.
SP6132 Wide Input, 300KHz Synchronous PWM Controller (c) Copyright 2004 Sipex Corporation
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6 7
8 9 10
Date: 8/4/04
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FUNCTIONAL DIAGRAM
5 COMP
100% Protection Logic
PULSES CLR COUNT 20 CLOCK
FAULT CLK RESET DOMINANT 10 BST
VCC Gm ERROR AMPLIFIER VPOS VCC 10 A SS 7 SOFTSTART INPUT POS REF VCC FAULT Gm
PWM LOOP VFBINT
9 GH SYNCHRONOUS DRIVER 8 SWN 2 GL
FAULT
VFB 4
R Q S 300 kHZ
QPWM
RAMP = 1.1V FAULT 0.4 V
CLK CLOCK PULSE GENERATOR
SS REFERENCE CORE
GL HOLD OFF
0.8V
REF OK
VCC 1
1.7 V
1.7 V ASYNC. STARTUP COMPARATOR 3 GND
THERMAL SHUTDOWN 145 C ON 135 C OFF
SET DOMINANT S
VPOS VFBINT
0.25 V +-
SHORT CIRCUIT DETECTION + -
Q
HICCUP FAULT FAULT REF OK
R
VCC
+ 4.25 V ON 4.05 V OFF + 2.50 VON 2.20 V OFF
VCC UVLO
POWER FAULT
VIN UVLO
CLK COUNTER 200ms Delay
6 UVIN
CLR REF OK
THERMAL AND SHORT CIRCUIT PROTECTION
UVLO COMPARATORS
THEORY OF OPERATION
General Overview
The SP6132 is a fixed frequency, voltage mode, synchronous PWM controller optimized for high efficiency. The part has been designed to be especially attractive for split plane applications utilizing 5V to power the controller and 3V to 12V for step down conversion. The heart of the SP6132 is a wide bandwidth transconductance amplifier designed to accommodate Type II and Type III compensation schemes. A precision 0.8V reference present on the positive terminal of the error amplifier permits the programming of the output voltage down to 0.8V via the VFB pin. The output of the error amplifier, COMP, compared to a 1.1V peak-to-peak ramp is responsible for trailing edge PWM control. This voltage ramp and PWM control logic are governed by the internal oscillator that accurately sets the PWM frequency to 300kHz.
Date: 8/4/04
The SP6132 contains two unique control features that are very powerful in distributed applications. First, asynchronous driver control is enabled during start up to prohibit the low side NFET from pulling down the output until the high side NFET has attempted to turn on. Second, a 100% duty cycle timeout ensures that the low side NFET is periodically enhanced during extended periods at 100% duty cycle. This guarantees the synchronized refreshing of the BST capacitor during very large duty ratios. The SP6132 also contains a number of valuable protection features. A programmable input (VIN) UVLO allows a user to set the exact value at which the conversion voltage is at a safe point to begin down conversion, and an internal VCC UVLO ensures that the controller itself has enough voltage to properly operate. Other pro(c) Copyright 2004 Sipex Corporation
SP6132 Wide Input, 300KHz Synchronous PWM Controller
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THEORY OF OPERATION: Continued tection features include thermal shutdown and short-circuit detection. In the event that either a thermal, short-circuit, or UVLO fault is detected, the SP6132 is forced into an idle state where the output drivers are held off for a finite period before a re-start is attempted.
Soft Start Thermal and Short-Circuit Protection
"Soft Start" is achieved when a power converter ramps up the output voltage while controlling the magnitude of the input supply source current. In a modern step down converter, ramping up the positive terminal of the error amplifier controls soft start. As a result, excess source current can be defined as the current required to charge the output capacitor. IVIN = COUT * DVOUT / DTSoft-start The SP6132 provides the user with the option to program the soft start rate by tying a capacitor from the SS pin to GND. The selection of this capacitor is based on the 10uA pull up current present at the SS pin and the 0.8V reference voltage. Therefore, the excess source can be redefined as: IVIN = COUT * DVOUT *10A / (CSS * 0.8V)
Under Voltage Lock Out (UVLO)
Because the SP6132 is designed to drive large NFETs running at high current, there is a chance that either the controller or power converter will become too hot. Therefore, an internal thermal shutdown (145C) has been included to prevent the IC from malfunctioning at extreme temperatures. A short-circuit detection comparator has also been included in the SP6132 to protect against the accidental short or sever build up of current at the output of the power converter. This comparator constantly monitors the positive and negative terminals of the error amplifier, and if the VFB pin ever falls more than 250mV (typical) below the positive reference, a short-circuit fault is set. Because the SS pin overrides the internal 0.8V reference during soft start, the SP6132 is capable of detecting short-circuit faults throughout the duration of soft start as well as in regular operation.
Handling of Faults:
The SP6132 contains two separate UVLO comparators to monitor the bias (VCC) and conversion (VIN) voltages independently. The VCC UVLO threshold is internally set to 4.25V, whereas the VIN UVLO threshold is programmable through the UVIN pin. When the UVIN pin is greater than 2.5V, the SP6132 is permitted to start up pending the removal of all other faults. Both the VCC and VIN UVLO comparators have been designed with hysteresis to prevent noise from resetting a fault.
Upon the detection of power (UVLO), thermal, or short-circuit faults, the SP6132 is forced into an idle state where the SS and COMP pins are pulled low and the gate drivers are held off. In the event of UVLO fault, the SP6132 remains in this idle state until the UVLO fault is removed. Upon the detection of a thermal or shor-circuit fault, an internal 200ms (typical) timer is activated. In the event of a short-circuit fault, a restart is attempted immediately after the 200ms timeout expires. Wereas, when a thermal fault is detected the 200ms delay continuously recycles and a re-start cannot be attempted until the thermal fault is removed and the timer expires.
Error Amplifier and Voltage Loop
As stated before, the heart of the SP6132 voltage error loop is a high performance, wide bandwidth transconductance amplifier. Because of the amplifier's current limited (+/-150A)
Date: 8/4/04 SP6132 Wide Input, 300KHz Synchronous PWM Controller (c) Copyright 2004 Sipex Corporation
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THEORY OF OPERATION: Continued transconductance, there are many ways to compensate the voltage loop or to control the COMP pin externally. If a simple, single pole, single zero response is required, then compensation can be a simple as an RC to ground. If a more complex compensation is required, then the amplifier has enough bandwidth (45 at 4 MHz) and enough gain (60dB) to run Type III compensation schemes with adequate gain and phase margins at cross over frequencies greater than 50kHz. The common mode output of the error amplifier is 0.9V to 2.2V. Therefore, the PWM voltage ramp has been set between 1.1V and 2.2V to ensure proper 0% to 100% duty cycle capability. The voltage loop also includes two other very important features. One is an asynchronous start up mode. Basically, the GL driver can not turn on unless the GH driver has attempted to turn on or the SS pin has exceeded 1.7V. This feature prevents the controller from "dragging down" the output voltage during startup or in fault modes. The second feature is a 100% duty cycle timeout that ensures synchronized refreshing of the BST capacitor at very high duty ratios. In the event that the GH driver is on for 20 continuous clock cycles, a reset is given to the PWM flip flop half way through the 21st cycle. This forces GL to rise for the remainder of the cycle, in turn refreshing the BST capacitor.
Gate Drivers
GATE DRIVER TEST CONDITIONS 90% GH(GL) 10% 90% GL(GH) 2V RISE TIME 10% NON-OVERLAP V(BST) GH Voltage V(SWN) V(VCC) GL Voltage 0V V(VIN) SWN Voltage -0V -V(Diode) V V(VIN)+V(VCC) BST Voltage V(VCC) TIME 2V FALL TIME
The SP6132 contains a pair of powerful 2 SOURCE and 1.5 SINK drivers. These state of the art drivers are designed to drive external NFETs capable of handling up to 30A. Rise, fall, and non-overlap times have all been minized to achieve maximum efficiency. All drive pins GH, GL & SWN are monitored continuously to ensure that only one external NFET is ever on at any given time.
Date: 8/4/04
SP6132 Wide Input, 300KHz Synchronous PWM Controller
(c) Copyright 2004 Sipex Corporation
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APPLICATIONS INFORMATION
Inductor Selection
There are many factors to consider in selecting the inductor including cost, efficiency, size and EMI. In a typical SP6132 circuit, the inductor is chosen primarily for value, saturation current and DC resistance. Increasing the inductor value will decrease output voltage ripple, but degrade transient response. Low inductor values provide the smallest size, but cause large ripple currents, poor efficiency and more output capacitance to smooth out the larger ripple current. The inductor must also be able to handle the peak current at the switching frequency without saturating, and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss. A good compromise between size, loss and cost is to set the inductor ripple current to be within 20% to 40% of the maximum output current. The switching frequency and the inductor operating point determine the inductor value as follows:
I PEAK = I OUT (max) +
I PP 2
and provide low core loss at the high switching frequency. Low cost powdered iron cores have a gradual saturation characteristic but can introduce considerable ac core loss, especially when the inductor value is relatively low and the ripple current is high. Ferrite materials, on the other hand, are more expensive and have an abrupt saturation characteristic with the inductance dropping sharply when the peak design current is exceeded. Nevertheless, they are preferred at high switching frequencies because they present very low core loss and the design only needs to prevent saturation. In general, ferrite or molypermalloy materials are better choice for all but the most cost sensitive applications. The power dissipated in the inductor is equal to the sum of the core and copper losses. To minimize copper losses, the winding resistance needs to be minimized, but this usually comes at the expense of a larger inductor. Core losses have a more significant contribution at low output current where the copper losses are at a minimum, and can typically be neglected at higher output currents where the copper losses dominate. Core loss information is usually available from the magnetic vendor. The copper loss in the inductor can be calculated using the following equation:
2 PL( Cu) = I L ( RMS ) RWINDING
L=
where:
VOUT (V IN (max) - VOUT ) VIN (max) FS Kr I OUT ( max)
Fs = switching frequency Kr = ratio of the ac inductor ripple current to the maximum output current The peak to peak inductor ripple current is:
I PP =
VOUT (VIN (max) - VOUT ) VI N (max) FS L
where IL(RMS) is the RMS inductor current that can be calculated as follows: IL(RMS) = IOUT(max) 1 + 1 3
Once the required inductor value is selected, the proper selection of core material is based on peak inductor current and efficiency requirements. The core must be large enough not to saturate at the peak inductor current
(
IPP
IOUT(max)
)
2
Date: 8/4/04
SP6132 Wide Input, 300KHz Synchronous PWM Controller
(c) Copyright 2004 Sipex Corporation
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APPLICATIONS INFORMATION: Continued
Output Capacitor Selection
FS = Switching Frequency D = Duty Cycle COUT = Output Capacitance Value
Input Capacitor Selection
The required ESR (Equivalent Series Resistance) and capacitance drive the selection of the type and quantity of the output capacitors. The ESR must be small enough that both the resistive voltage deviation due to a step change in the load current and the output ripple voltage do not exceed the tolerance limits expected on the output voltage. During an output load transient, the output capacitor must supply all the additional current demanded by the load until the SP6132CU adjusts the inductor current to the new value. Therefore the capacitance must be large enough so that the output voltage is help up while the inductor current ramps up or down to the value corresponding to the new load current. Additionally, the ESR in the output capacitor causes a step in the output voltage equal to the current. Because of the fast transient response and inherent 100% and 0% duty cycle capability provided by the SP6132CU when exposed to output load transient, the output capacitor is typically chosen for ESR, not for capacitance value. The output capacitor's ESR, combined with the inductor ripple current, is typically the main contributor to output voltage ripple. The maximum allowable ESR required to maintain a specified output voltage ripple can be calculated by: RESR VOUT IPK-PK where: VOUT = Peak to Peak Output Voltage Ripple IPK-PK = Peak to Peak Inductor Ripple Current The total output ripple is a combination of the ESR and the output capacitance value and can be calculated as follows:
The input capacitor should be selected for ripple current rating, capacitance and voltage rating. The input capacitor must meet the ripple current requirement imposed by the switching current. In continuous conduction mode, the source current of the high-side MOSFET is approximately a square wave of duty cycle VOUT/VIN. Most of this current is supplied by the input bypass capacitors. The RMS value of input capacitor current is determined at the maximum output current and under the assumption that the peak to peak inductor ripple current is low, it is given by: ICIN(rms) = IOUT(max) D(1 - D) The worse case occurs when the duty cycle D is 50% and gives an RMS current value equal to IOUT/2. Select input capacitors with adequate ripple current rating to ensure reliable operation. The power dissipated in the input capacitor is:
2 P = ICIN ( rms ) R ESR( CIN ) CIN
This can become a significant part of power losses in a converter and hurt the overall energy transfer efficiency. The input voltage ripple primarily depends on the input capacitor ESR and capacitance. Ignoring the inductor ripple current, the input voltage ripple can be determined by:
I OUT ( MAX )VOUT (VI N - VOUT ) FS C INV IN
2
VIN = I out (max) RE SR (CIN ) +
VOUT = IPP (1 - D) COUTFS
Date: 8/4/04
(
)
2
+ (IPPRESR)2
where:
SP6132 Wide Input, 300KHz Synchronous PWM Controller
(c) Copyright 2004 Sipex Corporation
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APPLICATIONS INFORMATION: Continued The capacitor type suitable for the output capacitors can also be used for the input capacitors. However, exercise extra caution when tantalum capacitors are considered. Tantalum capacitors are known for catastrophic failure when exposed to surge current, and input capacitors are prone to such surge current when power supplies are connected "live" to low impedance power sources.
MOSFET Selection
The total power losses of the top MOSFET are the sum of switching and conduction losses. For synchronous buck converters of efficiency over 90%, allow no more than 4% power losses for high or low side MOSFETs. For input voltages of 3.3V and 5V, conduction losses often dominate switching losses. Therefore, lowering the RDS(ON) of the MOSFETs always improves efficiency even though it gives rise to higher switching losses due to increased Crss. Top and bottom MOSFETs experience unequal conduction losses if their on time is unequal. For applications running at large or small duty cycle, it makes sense to use different top and bottom MOSFETs. Alternatively, parallel multiple MOSFETs to conduct large duty factor. RDS(ON) varies greatly with the gate driver voltage. The MOSFET vendors often specify RDS(ON) on multiple gate to source voltages (VGS), as well as provide typical curve of RDS(ON) versus VGS. For 5V input, use the RDS(ON) specified at 4.5V VGS. At the time of this publication, vendors, such as Fairchild, Siliconix and International Rectifier, have started to specify RDS(ON) at VGS less than 3V. This has provided necessary data for designs in which these MOSFETs are driven with 3.3V and made it possible to use SP6132 in 3.3V only applications. Thermal calculation must be conducted to ensure the MOSFET can handle the maximum load current. The junction temperature of the MOSFET, determined as follows, must stay below the maximum rating.
The losses associated with MOSFETs can be divided into conduction and switching losses. Conduction losses are related to the on resistance of MOSFETs, and increase with the load current. Switching losses occur on each on/off transition when the MOSFETs experience both high current and voltage. Since the bottom MOSFET switches current from/to a paralleled diode (either its own body diode or a Schottky diode), the voltage across the MOSFET is no more than 1V during switching transition. As a result, its switching losses are negligible. The switching losses are difficult to quantify due to all the variables affecting turn on/ off time. However, the following equation provides an approximation on the switching losses associated with the top MOSFET driven by SP6132.
PSH (max) = 12C rssV IN (max) I OUT (max) FS
where Crss = reverse transfer capacitance of the top MOSFET Switching losses need to be taken into account for high switching frequency, since they are directly proportional to switching frequency. The conduction losses associated with top and bottom MOSFETs are determined by:
PCH (max) = RDS (ON ) I OUT (max) D PCL(max) = R DS (ON ) I OUT (max) (1 - D)
where PCH(max) = conduction losses of the high side MOSFET PCL(max) = conduction losses of the low side MOSFET RDS(ON) = drain to source on resistance.
Date: 8/4/04
2
TJ ( max) = T A (max) +
where
PMOSFET (max) R JA
2
TA(max) = maximum ambient temperature PMOSFET(max) = maximum power dissipation of the MOSFET RJA = junction to ambient thermal resistance. RJA of the device depends greatly on the board layout, as well as device package. Significant
(c) Copyright 2004 Sipex Corporation
SP6132 Wide Input, 300KHz Synchronous PWM Controller
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APPLICATIONS INFORMATION: Continued thermal improvement can be achieved in the maximum power dissipation through the proper design of copper mounting pads on the circuit board. For example, in a SO-8 package, placing two 0.04 square inches copper pad directly under the package, without occupying additional board space, can increase the maximum power from approximately 1 to 1.2W. For DPAK package, enlarging the tap mounting pad to 1 square inches reduces the RJA from 96C/W to 40C/W.
Schottky Diode Selection
diode is equal to input voltage, and the diode must be able to handle the peak current equal to the maximum load current. The power dissipation of the Schottky diode is determined by PDIODE = 2VFIOUTTNOLFS where TNOL = non-overlap time between GH and GL. VF = forward voltage of the Schottky diode.
Loop Compensation Design
When paralleled with the bottom MOSFET, an optional Schottky diode can improve efficiency and reduce noises. Without this Schottky diode, the body diode of the bottom MOSFET conducts the current during the non-overlap time when both MOSFETs are turned off. Unfortunately, the body diode has high forward voltage and reverse recovery problem. The reverse recovery of the body diode causes additional switching noises when the diode turns off. The Schottky diode alleviates these noises and additionally improves efficiency thanks to its low forward voltage. The reverse voltage across the
Type III Voltage Loop Compensation GAMP (s) Gain Block
The open loop gain of the whole system can be divided into the gain of the error amplifier, PWM modulator, buck converter output stage, and feedback resistor divider. In order to crossover at the selected frequency FCO, the gain of the error amplifier has to compensate for the attenuation caused by the rest of the loop at this frequency.
PWM Stage GPWM Gain Block VIN VRAMP_PP Output Stage GOUT (s) Gain Block (SRESRCOUT+ 1) [S^2LCOUT+S(RESR+RDC) COUT+1]
VREF (Volts)
+ _
(SRz2Cz2+1)(SR1Cz3+1) SR1Cz2(SRz3Cz3+1)(SRz2Cp1+1)
VOUT (Volts)
Notes: RESR = Output Capacitor Equivalent Series Resistance. RDC = Output Inductor DC Resistance. VRAMP_PP = SP6132 Internal RAMP Amplitude Peak to Peak Voltage. Condition: Cz2 >> Cp1 & R1 >> Rz3 Output Load Resistance >> RESR & RDC
Voltage Feedback GFBK Gain Block R2 VFBK (Volts) (R1 + R2) VREF VOUT
or
SP6132 Voltage Mode Control Loop with Loop Dynamic
Definitions: Resr = Output Capacitor Equivalent Series Resistance Rdc = Output Inductor DC Resistance Vramp_pp = SP6132 internal RAMP Amplitude Peak to Peak Voltage Conditions: Cz2 >> Cp1 and R1 >> Rz3 Output Load Resistance >> Resr and Rdc
Date: 8/4/04 SP6132 Wide Input, 300KHz Synchronous PWM Controller (c) Copyright 2004 Sipex Corporation
10
APPLICATIONS INFORMATION: Continued The goal of loop compensation is to manipulate loop frequency response such that its gain crosses over 0db at a slope of -20db/dec. The first step of compensation design is to pick the loop crossover frequency. High crossover frequency is desirable for fast transient response, but often jeopardizes the system stability. Crossover frequency should be higher than the ESR zero but less than 1/5 of the switching frequency. The ESR zero is contributed by the ESR associated with the output capacitors and can be determined by: 1 2 COUT RESR
1/6.28 (RZ2) (CP1) 1/6.28 (RZ3) (CZ3) 1/6.28 (R1) (CZ3) 1/6.28(R22) (CZ2) 1/6.28 (R1) (CZ2)
Frequency (Hz)
When the output capacitors are of a Ceramic Type, the SP6132CU Evaluation Board requires a Type III compensation circuit to give a phase boost of 180 in order to counteract the effects of an under damped resonance of the output filter at the double pole frequency.
Gain (dB)
Error Amplify Gain Bandwidth Product Condition: C22 >> CP1, R1 >> RZ3
Z(ESR) =
20 Log (RZ2/R1)
The next step is to calculated the complex conjugate poles contributed by the LC output filter, 1 2 L COUT
Bode Plot of Type III Error Amplify Compensation.
P(LC) =
Inductance (uH) 2.7 2.7 3.3 1.2 1.2 1.5 1.9
Manufacturer/Part No.
Easy Magnet SC5018-2R7M TDK RLF12560T-2R7N110 Coilcraft DO5010P-332HC Easy Magnet SC5018-1R2M Inter-Technical SC4015-1R2M
Series R mOhms 4.30 4.50 8.60 1.96 4.37 4.00 3.60
INDUCTORS - SURFACE MOUNT Inductor Specification Isat Size Inductor Type (A) LxW(mm) Ht.(mm) 12.0 12.6x12.6 4.5 Shielded Ferrite Core 12.2 12.5x12.8 6.0 Shielded Ferrite Core 17.0 14.7x15.2 8.0 Unshielded Ferrite Core
Shielded Ferrite Core Shielded Ferrite Core Unshielded Ferrite Core Shielded Ferrite Core
Manufacturer Website
www.easymagnet.com www.tdk.com www.coilcraft.com www.easymagnet.com www.inter-technical.com www.coilcraft.com www.tdk.com
Coilcraft DO5010P-152HC
TDK RLF12560T-1R9N120
Capacitance(u F) 22 47
Manufacturer/Part No.
TDK C3225X5R1C226M TDK C3225X5R0J476M
20.0 12.6x12.6 4.5 17.0 10.0x10.0 3.8 25.0 14.7x15.2 8.0 13.2 12.5x12.8 6.0 CAPACITORS - SURFACE MOUNT Capacitor Specification Size ESR Ripple Current ohms (max) (A) @ 45C LxW(mm) Ht.(mm) 0.002 4.00 3.2x2.5 2.0 0.002 4.00 3.2x2.5 2.5
Voltage (V) 16.0 6.3
Capacitor Type X5R Ceramic X5R Ceramic
Manufacturer Website
www.tdk.com www.tdk.com
MOSFETS - SURFACE MOUNT MOSFET N-Channel N-Channel Manufacturer/Part No.
Fairchild Semi FDS7088N3 Vishay Si4336DY
RDS(on) ohms (max) 0.005 0.004
ID Current (A) 21.0 25.0
MOSFET Specification Qg Voltage nC (Typ) nC (Max) (V) 37.0 48.0 30.0 32.0 50.0 30.0
Foot Print SO-8 SO-8
Manufacturer Website
www.fairchildsemi.com www.Vishay.com
Note: Components highlighted in bold are those used on the SP6132 Evaluation Board.
Table 1. Input and Output Stage Components Selection Charts.
Date: 8/4/04 SP6132 Wide Input, 300KHz Synchronous PWM Controller (c) Copyright 2004 Sipex Corporation
11
APPLICATIONS INFORMATION: Continued
SP6132EB Component Placement
SP6132EB PC Layout Top Side
SP6132EB PC Layout Bottom Side
Date: 8/4/04
SP6132 Wide Input, 300KHz Synchronous PWM Controller
(c) Copyright 2004 Sipex Corporation
12
PACKAGE: 10 PIN MSOP
D e1
O1
E/2
R1 R Gauge Plane
O
E
E1
L2 Seating Plane
1 2
O1
L L1
00
e Pin #1 indentifier must be indicated within this shaded area (D/2 * E1/2)
10-PIN MSOP JEDEC MO-187 (BA) Variation A A1 A2 b c D E E1 e e1 L L1 L2 N R R1 O O1
Dimensions in (mm) MIN 0 0.75 0.17 0.08 NOM MAX 0.85 3.00 BSC 4.90 BSC 3.00 BSC 0.50 BSC 2.00 BSC 0.4 0.60 0.95 REF 0.25 BSC 10 0.07 0.07 0 5 8 15 0.80 1.1 0.15 0.95 0.27 0.23
(b)
WITH PLATING
c
BASE METAL
A2 b A1
A
1
10-PIN MSOP
SP6132 Wide Input, 300KHz Synchronous PWM Controller (c) Copyright 2004 Sipex Corporation
Date: 8/4/04
13
ORDERING INFORMATION
Part Number Top Mark Temperature Package SP6132CU ............................ SP6132CU....................0C to +70C ....................... 10 Pin MSOP SP6132CU/TR ...................... SP6132CU....................0C to +70C ....................... 10 Pin MSOP SP6132CU-L ......................... SP6132CU....................0C to +70C ... (Lead Free) 10 Pin MSOP SP6132CU-L/TR ................... SP6132CU....................0C to +70C ... (Lead Free) 10 Pin MSOP SP6132EU ............................ SP6132EU..................-40C to +85C ..................... 10 Pin MSOP SP6132EU/TR ....................... SP6132EU..................-40C to +85C ..................... 10 Pin MSOP SP6132EU-L ......................... SP6132EU..................-40C to +85C .. (Lead Free) 10 Pin MSOP SP6132EU-L/TR ................... SP6132EU..................-40C to +85C .. (Lead Free) 10 Pin MSOP
/TR = Tape and Reel Pack quantity is 2500 for MSOP.
Corporation
ANALOG EXCELLENCE
Sipex Corporation Headquarters and Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Date: 8/4/04
SP6132 Wide Input, 300KHz Synchronous PWM Controller
(c) Copyright 2004 Sipex Corporation
14

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